1. Field of the Invention
The present invention relates generally to arm electronics (AE) in disk drives, and more particularly to methods and apparatus for gradually decreasing the supply current demand in the AE for write-to-read mode transitions to reduce signal transients.
2. Description of the Related Art
Conventional disk drives have write-to-read mode recovery times that are either too long or, if reduced, allow for unreliable data detection due to unsettled signal transients generated during write-to-read mode transitions and the less than infinite power supply rejection ratios (PSRRs) of preamplifiers used in read mode circuitry.
To illustrate, FIG. 1 is a block diagram of relevant components of a conventional disk drive 100 having conventional arm electronics (AE) 104. AE 104 is typically embodied on a single integrated circuit (IC) chip. AE 104 includes reference circuitry 108, a controller 110, read mode circuitry 112, and write mode circuitry 114. Disk drive 100 has a power supply 102 which supplies power to AE 104 through a cable 106 (e.g., a flex connector). More particularly, power supply 102 provides supply voltages +Vcc and −Vee via cable 106 at conductive pads of a power supply input 107. Supply voltages +Vcc and −Vee used by AE 104 may be, for example, +5 volts and −5 volts, respectively. Reference circuitry 108 provides a reference voltage VREF which is also used in AE 104.
Read mode circuitry 112 and write mode circuitry 114 are separate circuits which are optimized for their specific functions so that the overall power dissipation in AE 104 is low. Read mode circuitry 112 is coupled to a plurality of read heads, such as a read head 120, for reading data from a plurality of disks, such as disk 106, during a read mode of operation. In the read mode, the basic functions of read mode circuitry 112 are active whereas the basic functions of write mode circuitry 114 are generally inactive. Read data are read from disk 106 by read head 120, passed to read mode circuitry 112, and provided at a read output 116 for further processing. During steady-state read mode, a read mode supply current is drawn from power supply 102 through cable 106. The read mode supply current is less than the write mode supply current. The reason for this difference is because during the write mode where write mode circuitry 114 is active, some portions of read mode circuitry 112 still remain active. The read mode supply current may be, for example, about 60 milliamps.
Read mode circuitry 112 includes, as shown in FIG. 3, a preamplifier 302 which is coupled to the supply voltages +Vcc and −Vee. During the read mode, preamplifier 302 receives very small signals from read head 120 (FIG. 1) at a preamplifier input 304 and amplifies these signals to produce amplified signals at a preamplifier output 306. Preamplifier 302 has a high gain which makes read mode circuitry 112 extremely sensitive. If the supply voltages +Vcc and −Vee are not sufficiently stable, the amplified signals at preamplifier output 306 will be adversely affected and data detection will be unreliable.
Referring back to FIG. 1, write mode circuitry 114 is coupled to a plurality of write heads, such as a write head 122, for writing data to disk 106 during a write mode of operation. In the write mode, basic functions of write mode circuitry 114 are active whereas the basic functions of read mode circuitry 112 are generally inactive. Write data are fed into write mode circuitry 114 at a write input 118, passed to write head 122, and written to disk 106. During steady-state write mode, a write mode supply current is drawn from power supply 102 through cable 106. The write mode supply current is greater than the read mode supply current, for the reason previously stated above. The write mode supply current may be, for example, about 210 milliamps.
Controller 110 of FIG. 1 provides a read/write (R/W) mode signal 124 for activation and deactivation of read and write mode circuitry 112 and 114 during disk drive operation. In particular, when controller 110 instructs AE 104 to transition from the write mode to the read mode, an abrupt change from the write mode supply current to the read mode supply current occurs. This abrupt change in current is illustrated in FIG. 4 by a write-to-read current transition requirement 402. As shown, write-to-read current transition requirement 402 reflects a step or step-like discontinuity. In this particular example, the abrupt current change is about 150 milliamps, which is the difference between the write mode supply current of about 210 milliamps and the read mode supply current of about 60 milliamps.
In response to this step or step-like discontinuity, cable 106 (FIG. 1) imposes undesirable fluctuations in voltage at power supply input 107 of AE 104. The reason this occurs is because cable 106 has inherent parasitic series inductance and capacitance as well as power supply decoupling capacitors placed at various locations in and along cable 106 which form a cable network of R-L-Cs (i.e., resistors, inductors, and capacitors). In FIG. 2, an example of a lumped-parameter model 200 of this cable network is shown. In FIG. 5, an example of write-to-read supply voltage transition signals 502 and 504 (+Vcc and −Vee, respectively) having voltage fluctuations 506 is shown. Thus, supply voltage transients are produced due to the non-ideal connector coupled between AE 104 and power supply 102.
Due to such voltage fluctuations, preamplifier output 306 of FIG. 3 will exhibit an undesirable response since its power supply rejection ratio (PSRR) is finite. In FIG. 6, a preamplifier output signal 602 having undesirable output fluctuations 604 due to the voltage fluctuations 506 of FIG. 5 is shown. Due to such fluctuations, any data detection at the beginning of the read mode will be corrupted or unreliable. Since unreliable data detection is not acceptable, the transition time between write and read modes (i.e., the “write-to-read recovery time”) which is imposed by subsequent detection circuitry is longer than it would otherwise have to be. It is generally desirable and advantageous, however, to keep the write-to-read recovery time in a disk drive as short as possible so that it can operate quickly and allow for a large amount of data to be written to a disk over a given time period.
In the prior art, improving circuit PSRR has been approached as a means to mitigate transient recovery problems, but such an approach can only correct the problem to a limited degree. Another approach would be to include additional reference circuitry in the AE to regulate supply voltage for the sensitive read circuitry. However, such additional circuitry consumes additional power and imposes difficult design challenges due to reduced voltage headroom available to the sensitive read circuitry.